Monolithic silicon chips are hitting physical manufacturing size limits and soaring defect costs; the DICE modeling framework provides end-to-end physical-layer simulation for modular multi-chiplet packaging.

For six decades, Moore's Law drove microelectronics by shrinking transistors on monolithic silicon dies. Today, advanced processor dies have grown so massive that fabrication yields plummet, making giant single-die chips economically unsustainable.
The semiconductor industry is rapidly shifting to chiplets—disaggregating processors into smaller, modular silicon dies connected via high-density packaging. However, modeling high-speed inter-chiplet signal integrity, latency, and thermal cross-talk presented a severe engineering blind spot.
DICE (Detailed Inter-Chiplet End-to-End PHY Modeling) introduces an architectural simulation platform that accurately models the physical layer (PHY), die-to-die interconnect wires, and signal loss across advanced 2.5D and 3D packaging substrates.
DICE enables semiconductor architects to optimize next-generation AI accelerators and multi-core server processors, slashing design iterations and accelerating the transition to modular chiplet computing.
DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation
Scaling monolithic multicores is increasingly constrained by power/thermal limits, yield, and rising manufacturing and testing costs. Chiplet designs address these challenges by partitioning large dies into smaller parts (typically multiple core-complex dies and an I/O die) linked via high-bandwidth physical fabrics (PHY). As bandwidth and wiring density scale, however, these short-reach links are pushed closer to their signal-integrity limits, increasing susceptibility to noise, crosstalk, and channel loss, motivating stronger link-level reliability mechanisms such as forward error correction (FEC). Despite this trend, state-of-the-art simulation infrastructures often approximate inter-chiplet links using oversimplified, fixed-latency models. Such abstractions overlook the inherently dynamic, runtime-dependent behavior of the PHY -- including channel conditions (e.g., signal-to-noise ratio shifts, signal crosstalk, clock jitter), iterative decoder convergence and packet retransmissions, and application dynamics (e.g., LLC-misses that travel across chiplet boundaries) -- all of which are hard to determine offline. We show that neglecting these effects distorts inter-chiplet packet-level timing and high-level performance metrics such as IPC, leading to off-trend simulation results. We present DICE, an in-simulation, runtime PHY modeling in gem5 that captures the end-to-end inter-chiplet datapath, including QC-LDPC encoding/decoding, PAM4 modulation, lossy-channel transmission, LLR-based demodulation, adaptive packet re-sending, and PHY-level flow control between chiplets.
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